The importance of selecting the right package for a chip

There are a number of elements in the electronics world which have a higher priority than was the case some years ago – and it's certainly the case when it comes to packaging leading edge chips.

Patrick McNamee, vp of silicon operations for envelope tracking (ET) technology pioneer Nujira, explained: "The days have gone when you could finish a design, then look at what kind of package – bga or tqfp – you could put it in. Companies now have to know the package from the start of the design process. Even with our 'Gen 1' product, we were already pushing the design rules when it came to packaging."

'Gen 1' is the Coolteq.L NCT-L1300 ET power supply chip, which entered volume production earlier in 2013. This device is already being upgraded, with the working title of 'Gen 2'. And the Cambridge based company has to decide how to package it.

"We certainly had some packaging challenges with Gen 1," McNamee observed, "and these have sharpened with the latest design. Gen 2 will support higher bandwidths and more power in a smaller footprint, but has to be thin enough to go into a smartphone and meet the phone builder's cost targets. The process will be a lot more challenging and we are thinking very carefully about how we proceed."

The L1300 comes in a wafer level chip scale package with a 0.4mm ball pitch. "It's essentially a fast very high bandwidth op amp," McNamee pointed out. According to the plans, Gen 2 will support twice the bandwidth of the L1300, but will be manufactured using the same process geometry. "With twice the bandwidth," McNamee continued, "Gen 2 will create a harsh electrical environment and we will have to control the parasitics more closely. While the die is getting smaller as we simplify the design, we still have to deal with a peak power of around 1.2W." With the device more susceptible to stray inductance, McNamee said the packaging challenges increase.

Parasitics can be controlled by careful placement of capacitors around the device. Ideally, those capacitors would be on chip. "But we can't get large enough capacitors inside the package, otherwise the die would be too large. That means we have to think about routing; Gen 2 is already I/O constrained."

So where does Nujira go when it comes to deciding on packaging technology? One approach is to enlist the help of specialist packaging houses and Nujira has selected ASE as its production packaging partner for Coolteq.L devices. As part of the deal, ASE is helping Nujira to achieve its packaging objectives quickly and effectively. McNamee said: "Moving into volume production is a huge step, so it is critical that we select world class supply chain partners. As the world's largest semiconductor packaging and test company, ASE offers us the expertise, capacity, reliable quality and cycle time we need to address the high volume, fast moving smartphone market."

Nujira is currently using ASE's flip chip wafer level chip scale packaging (wlcsp) technology for its Coolteq.L ET chips, but that's not likely to continue with Gen 2. WLCSP has been used broadly for nearly a decade and has developed into a reliable packaging technology with high yield. But it has drawbacks, including routing parasitics. "Some packages will just not be suitable for Gen 2," McNamee stated. "Any way we do things, we will not get enough control to give repeatable performance from the device. A lead frame helps, but you still can't get the performance you need."

The benefit of wlcsp for Gen 1 parts is that it's cost effective and there are no bond wires. "So we can control the parasitics because we control the routing. But we don't have control over access to the outside world."

A possible solution is flip chip system in package (fcsip). This would require Nujira to build a module, a more costly approach with some routing issues, but a choice which brings control over placement of critical passives. Other issues include device height and a larger than ideal footprint. "We have more control with this technology, but it's quite expensive," McNamee observed, "and customers get worried about 'margin stacking'." FCSIP would allow some passives to be integrated into the device, but margin stacking reflects the 'handling charge' for this. "But it has potential," McNamee admitted.

Two variations on the fcsip theme offer a bit more hope. Copper pillar fcsip is offered by ASE as a way to meet demand for smaller, thinner, lighter, and higher performance packages. According to ASE, this is the most effective method for fine pitch interconnection in flip chip packages – enabling ball to ball distances of 0.2mm.

"We'll be looking at this," McNamee commented, "because Gen 2 will be I/O constrained. But our device will need to use a 0.4mm pitch, otherwise pcb costs will be driven up. So we need to use something like an interposer to increase the pitch."

The other version is two sided copper pillar, with discretes on the bottom. "This has a lot of advantages," McNamee said. "We have looked at this in depth and might come back to it at some point. It ticks a lot of boxes, but it's more expensive."

The ideal solution for Nujira would be some process which supports embedded components – whether the die itself or passives. "There aren't many companies running such processes in volume," McNamee observed. "They are expensive and exotic, but do provide a solution to the electrical problems. However, those running them tend to be companies with cheap dice who can afford to lose some in the packaging process."

Embedding passives within a substrate inside the package means no bond wires, control of passives placement and hence, good parasitic control. A similar approach can see a die embedded within the substrate, but questions remain about yield. Another variant is embedding integrated passive devices, or IPD, within the substrate. "IPD is very interesting," McNamee said. "But one of the challenges is getting the correct value of capacitors and inductors at 2.4GHz; you don't always get what you expect."

A solution to this challenge is being developed by French company IPDIA, a spin off from NXP. "It's an expensive approach," McNamee said, "but it's a very good process – it's the equivalent of FinFETs for passives."

With a choice of packaging approaches being narrowed down, Nujira still has one big issue on the table – thermal management. With a device handling a peak power of 1.2A, heat is an issue. "We're still looking at it," McNamee admitted. "We're still running models, but should have the results in the next few weeks. Then, we can finalise our decision."

Nujira started looking at Gen 2 at the end of 2012. "It's taken six months to research, consider the options and narrow the choices," McNamee concluded. "The process should be complete by the end of October. It has taken a long time, but it's a challenging project."